Posts about verilog code for 8-bit adder/subtractor written by kishorechurchil. (Serial In Parallel Out). Verilog Code for Parallel In Parallel Out. The 74LV165A is an 8-bit parallel-load or serial-in shift register with complementary serial. Allows parallel-to-serial converter expansion by tying the output Q7.
Mini Project on 4 BIT SERIAL MULTIPLIER. 1. Page 1 of 19 4 BIT SERIAL MULTIPLIER A Project Based LAB Dissertation LAB Title: Design with CPLDs and FPGAs Submitted by Mr. J.NAGA SAI (Reg. 150040317) LAB Instructors Mr. B.Kali vara Prasad (Section Instructor) Mr.
Narasimha Nayak Dr.A. Kiran Kumar Mr.M.Venkateswara rao Department of ECE, KL University Vaddeswaram, Guntur, AP – 522502 A.Y. 2016-17. Page 2 of 19 Department of Electronics and Communication Engineering KL University Vaddeswaram, Guntur, AP – 522502 CERTIFICATE This is to certify that the project entitled '4-BIT SERIAL MULTIPLIER ' is a piece of work done by J.NAGA SAI(150040317) students of II B.Tech. (ECE), during the First semester of academic year 2016-2017, of Department of Electronics and Communication Engineering of KL University, Vaddeswaram, Guntur, A.P., INDIA. Course Coordinator Signature of the H.O.D (Dr.
![8 Bit Serial To Parallel Converter Verilog Code For 4 8 Bit Serial To Parallel Converter Verilog Code For 4](http://1.bp.blogspot.com/-0_hiDG3vS10/UeN0EnBJ7uI/AAAAAAAAAkk/ZTeaKG8OUrQ/s1600/img7-15-2013-9.29.24+AM.jpg)
Fazal Noorbasha) (Dr.ASCS Sastry). Page 3 of 19 Declaration by the Students We declare that the project entitled, “4-BIT SERIAL MULTIPLIER” is our own work conducted under the esteemed guidance of Mr. B.Kali vara Prasad (Section Instructor) Mr. Narasimha Nayak Dr.A. Kiran Kumar,Mr.M.Venkateswara rao at the Department of Electronics and Communication Engineering of KL University, Vaddeswaram, Guntur, A.P., INDIA.
J.NAGA SAI (Reg. 150040317).
Page 4 of 19 Acknowledgements Working on this Project based Lab is certainly a memorable and enjoyable event in our life. We have learned a lot of interesting new things that have broadened my view of the technology field.
In here, we would like to offer our appreciation and thanks to several grateful and helpful individuals. Without them, this work could not have been completed and the experience would not be so enjoyable. We are very grateful to our esteemed Professors Dr. Fazal Noorbasha (Course Coordinator), Mr.B.Kali vara Prasad (Section Instructor)Mr. Narasimha NayakDr.A. Kiran Kumar Mr.M.Venkateswara raoDepartment of ECE, KL University, Vaddeswaram, Guntur, A.P., INDIA, for their valuable guidance and creative suggestions that helped us to complete this Lab project.
Furthermore, we want to offer our thanks to Dr. ASCS Sastry, Professor & Head, Department ECE, KL University, Vaddeswaram, Guntur, A.P., INDIA, for providing the required facilities to carry out the project work successfully. We would like to thank all those helped us directly or indirectly during this project work. J.NAGA SAI (Reg. 150040317).
Page 5 of 19 4 BIT SERIAL MULTIPLIER INDEX Content Name Page no 1.ABSTRACT 6 2.INTRODUCTION 7 3. MULTIPLICATION ALGORITHM 8 4.PROCEDURE: 11 PROJECT VERILOG CODE 15 TEST BENCH 16 7.OUTPUT: 19 8.RESULT: 19 9.
References: 19. Page 6 of 19 1.ABSTRACT Bit-serial arithmetic is attractive in view of it is smaller pin count, reduced wirelength, and lower floor space requirement in VLSI.
In fact,the compactness of the design may allow us to run a bit- serial multiplier at a clock rate high enough to make the unit almost competitive with much more complex designs with regard to speed. In addition, in certain application contexts inputs are supplied bit-serially anyway. In such a case, using a parallel multiplier would be quite wasteful, since the parallelism may not lead to any speed benefit. Furthermore, in applications that call for a large number of independent multiplications, multiple bit-serial multiplier may be more cost- effective than a complex highly pipelined unit. Bit-serial multipliers can be designed as systolic arrays: synchronous arrays of processing element that are interconnected by only short, local wires thus allowing very high clock rates. Let us begin by introducing a semi systolic multiplier, so named because its design involves broadcasting a single bit of the multiplier x to a number of circuit element, thus violating the “short, local wires” requirement of pure systolic design.
Page 7 of 19 2.INTRODUCTION Multipliers play an important role in today’s digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets – high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier thus making them suitable for various high speed, low power and compact VLSI implementation. The common multiplication method is “add and shift” algorithm. In parallel multipliers number of partial products to be added is the main parameter that determines the performance of the multiplier. To reduce the number of partial products to be added, Modified Booth algorithm is one of the most popular algorithms.
To achieve speed improvements Wallace Tree algorithm can be used to reduce the number of sequential adding stages. Further by combining both Modified Booth algorithm and Wallace Tree technique we can see advantage of both algorithms in one multiplier. However with increasing parallelism, the amount of shifts between the partial products and intermediate sums to be added will increase which may result in reduced speed, increase in silicon area due to irregularity of structure and also increased power consumption due to increase in interconnect resulting from complex routing. On the other hand “serialparallel” multipliers compromise speed to achieve better performance for area and power consumption.
The selection of a parallel or serial multiplier actually depends on the nature of application. In this lecture we introduce the multiplication algorithms and architecture and compare them in terms of speed, area, power and combination of these metrics. Page 8 of 19 3. MULTIPLICATION ALGORITHM The multiplication algorithm for an N bit multiplicand by N bit multiplier is shown below: Y= Yn-1 Yn-2.Y2 Y1 Y0 Multiplicand X= Xn-1 Xn-2. X2 X1 X0 Multiplier GENERALLY Y= Yn-1 Yn-2.Y2 Y1 Y0 X= Xn-1 Xn-2. X2 X1 X0 Yn-1X0 Yn-2X0 Yn-3X0 Y1X0 Y0X0 Yn-1X1 Yn-2X1 Yn-3X1 Y1X1 Y0X1 Yn-1X2 Yn-2X2 Yn-3X2 Y1X2 Y0X2. Yn-1Xn-2 Yn-2X0 n-2 Yn-3X n-2 Y1Xn-2 Y0Xn-2 Yn-1Xn-1 Yn-2X0n-1 Yn-3Xn-1 Y1Xn-1 Y0Xn-1 - -P2n-1 P2n-2 P2n-3 P2 P1 P0.
Page 9 of 19 DIFFERENT TYPES OF MULTIPLIERS Serial/Parallel Multiplier One operand is fed to the circuit in parallel while the other is serial. N partial products are formed each cycle. On successive cycles, each cycle does the addition of one column of the multiplication table of M.N PPs.
The final results are stored in the output register after N+M cycles. While the area required is N- 1 for M=N.
Shift and Add Multiplier Depending on the value of multiplier LSB bit, a value of the multiplicand is added and accumulated. At each clock cycle the multiplier is shifted one bit to the right and its value is tested. If it is a 0, then only a shift operation is performed. If the value is a 1, then the multiplicand is added to the accumulator and is shifted by one bit to the right. After all the multiplier bits have been tested the product is in the accumulator. The accumulator is 2N (M+N) in size and initially the N, LSBs contains the Multiplier. The delay is N cycles maximum.
This circuit has several advantages in asynchronous circuits. Array MULTIPLIER Array multiplier is well known due to its regular structure. Multiplier circuit is based on add and shift algorithm. Each partial product is generated by the multiplication of the multiplicand with one multiplier bit.
The partial product are shifted according to their bit orders and then added. The addition can be performed with normal carry propagate adder. N-1 adders are required where N is the multiplier length. Page 10 of 19 EXAMPLE: MULTIPLICATION IN DETAIL:.
![8 Bit Serial To Parallel Converter Verilog Code For 4 8 Bit Serial To Parallel Converter Verilog Code For 4](http://4.bp.blogspot.com/-6lsfhx_aPuw/T3f8PRNXRlI/AAAAAAAACK8/IgKnnw9qTew/s1600/Untitled.png)
Page 11 of 19 4.PROCEDURE:. Page 12 of 19 Binary Multiplication: In the binary number system the digits, called bits, are limited to the set. The result of multiplying any binary number by a single binary bit is either 0, or the original number.
This makes forming the intermediate partial-products simple and efficient. Summing these partial- products is the time consuming task for binary multipliers. One logical approach is to form the partial-products one at a time and sum them as they are generated.
Often implemented by software on processors that do not have a hardware multiplier, this technique works fine, but is slow because at least one machine cycle is required to sum each additional partial-product. For applications where this approach does not provide enough performance, multipliers can be implemented directly in hardware.
COMPONENTS IN A 4 BIT SERIAL MULTIPLIER: 1. HALF ADDER 3. FULL ADDER 1.
AND GATE: The AND gate is a basic logic that implements logical conjunction – It behaves according to the truth table Logic Diagram TRUT H TABLE:. Page 13 of 19 Workinng: In this gate if either of the inputs is low (0), then the output is also low, but if all the inputs are high (1) the output will also be high (1). 2.HALF ADDER Half adder is a combinational arithmetic circuit that adds two numbers and produces a sum bit (S) and carry bit (C) as the output.
If A and B are the input bits, then sum bit (S) is the X-OR of A and B and the carry bit (C) will be the AND of A and B. Logic Diagram: TRUTH TABLE:. Page 14 of 19 Working: The half adder adds two one-bit binary numbers (AB). The output is the sum of the two bits (S) and the carry (C). Note how the same two inputs are directed to two different gates. The inputs to the XOR gate are also the inputs to the AND gate.